1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including an MOS transistor, in particular, to a technique effectively applied to a layout structure in consideration of a transistor characteristic varying depending on a stress-strain applied by a shallow trench isolation (STI).
2. Description of the Related Art
With the recent miniaturization of a transistor, an STI structure has been widely used as a technique of isolating MOS transistors from each other. In a CMOS device fabricated by a refined process, a phenomenon that the MOS transistor demonstrates a variation in a threshold voltage, current drivability, and the like under a stress applied by the STI has been confirmed. In particular, for the CMOS device including a plurality of transistors in a predetermined region surrounded by the STI, the stress applied by the STI is varied for each of the plurality of transistors depending on the position of the transistor in the predetermined region. More specifically, because a diffusion area, a gate, or the like has an irregular pattern in an end area of the predetermined region, the transistor is more remarkably affected by the stress from the STI as compared with that in a central area. With an increase in the degree of integration and miniaturization, less suppression of the variation is requested.
The relation between the STI structure and the transistor characteristic is described in, for example, the following patent publications.
First, Japanese Patent Application Laid-open No. 2006-190727 (hereinafter, referred to as Patent Document 1) describes a variation in effect of a stress generated in an STI structure on each of a P-channel transistor and an N-channel transistor. The stress is applied by the STI to a device active region in a compression direction. As a result, an electron mobility decreases, whereas a hole mobility increases. In view of the problem, Patent Document 1 discloses that full (100%) transistor performance (Ids characteristic) can be obtained by increasing a distance from a device isolation region to a channel region in a gate length direction in the N-channel transistor.
Japanese Patent Application Laid-open No. 2005-101453 (hereinafter, referred to as Patent Document 2) discloses a semiconductor device including an extra dummy cell region provided in an outer peripheral area of a memory cell array so as to absorb a variation in processing size of the other cells.
Furthermore, Japanese Patent Application Laid-open No. 2002-76148 (hereinafter, referred to as Patent Document 3) discloses a technique of reducing a variation in size of a memory cell array in a non-volatile memory in the following manner. A width of a device isolation region and an interval between floating gates are increased only in a boundary area between an end area of a memory cell array and an inner area of the memory cell array. In addition, a width of a device region is increased only in the end area of the memory cell array.
The above description is summarized as follows. According to Patent Documents 1 and 3, an area of each of outermost cells 2 is increased in directions as indicated with arrows as compared with an inner cell 1 in an array 3, as illustrated in FIG. 8. According to Patent Document 2, an invalid area 2d is required as illustrated in FIG. 9. In other words, in all the Patent Documents 1 to 3 described above, a variation in transistor characteristic of the whole array is reduced at the sacrifice of the area of the outermost cells 2 or 2d. Herein, a unit cell is a single cell transistor or a region of a minimum unit circuit to be repeated. For example, in the case of an SRAM memory, six transistors form a single cell. The unit cell, which includes the transistors constituting the cell and a margin from a neighboring cell, is schematically represented by a single rectangular. The unit cells arranged in a plurality of matrices are referred to as an array.
According to Patent Documents 1 and 3, however, a device region in the end area of the array is increased to correspondingly increase a chip size. Similarly, in Patent Document 2, the dummy region is required to be provided in the end area of the array, which prevents a chip-size reduction from being achieved.